192194 - Elect Design and Analy Engr 4
6 Months
Chipton-Ross is seeking 2 Electrical Design and Analysis Engr 4's for an opportunity in Tukwila, WA.

Leads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic products. Leads development of high-level and detailed designs consistent with requirements and specifications. Leads reviews of testing and analysis activity to assure compliance to requirements. Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements. Leads activities in support of Supplier Management with make/buy recommendations and other technical services. Coordinates engineering support throughout the lifecycle of the product. Plans research projects to develop concepts for future product designs to meet projected requirements. Works under minimal direction.

We are seeking experienced integrated circuit (IC) layout engineers to implement custom analog/mixed-signal circuits in state-of-the-art CMOS (=22nm) and SiGe semiconductor fabrication processes. The qualified candidate will have experience performing custom IC layout to achieve tight matching, high speed, low noise, and low power consumption. Circuits for custom layout may include analog or digital standard cells, resistors and capacitors, IO cells, ESD structures, and SRAM leaf cells.
Tasks/responsibilities include:
• Working closely with IC / chip design team on block-level and chip-level floor-planning
• Performing cell-level layout, block-level layout, and chip assembly
• Performing physical verification including design rule checks (DRC), layout vs. schematic (LVS) checks, and electrical rule checks (ERC)
• Perform / support parasitic extraction (PEX) and analysis
• Drive continued improvement of layout practices and procedures

• 6+ years of experience in full-custom analog/mixed-signal IC layout
• Thorough understanding of industry-standard electronic design automation (EDA) tools for IC layout and physical verification – e.g. those from Cadence, Mentor Graphics, and Synopsys
• Experience with standard cell development and/or familiarity with structured, pitched, or arrayed layout
• Knowledge of performance analog and high-power layout techniques
• Experience exercising and debugging the IC verification flow (DRC, LVS, XOR, PEX, etc.)
• Demonstrated successful IC designs implemented in advanced commercial semiconductor fabrication process technologies – e.g.. <22nm FinFET), silicon-on-insulator (SOI), and/or silicon germanium (SiGe) processes.
• Experience with layout techniques for managing IR drop, RC delay, electromigration, self heating and coupling capacitance

Preferred Qualifications:
• Experience with Radiation-Hardened By Design (RHBD) layout techniques
• Experience with scripting to automate IC layout (e.g. SKILL, Perl, Python)
• Experience with experimental process technologies (e.g. Gate-all-around FETs (GAAFETs))

Accredited Bachelor, Master or Doctorate degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry.

Possible domestic trave

Full-Time/First Shift

Can be virtual but possible travel to onsite location as needed.

Employment will be contingent on clearing a drug screen and background check. Both must clear prior to start date.

Dan Mulvihill
420 Culver Boulevard
Playa Del Rey, CA 90293

Phone: (310) 414-7800 x286 or (800) 927-9318 x286

To ensure compliance with President Biden’s September 9, 2021 executive order, the client is implementing a new requirement for U.S.-based employees to either show proof of being fully vaccinated from COVID-19, or have an approved reasonable accommodation (based on a disability/medical condition or sincerely held religious belief) exempting them from the requirement, by December 8, 2021 (timing may vary in some states). Individuals who are unable to meet COVID-19 requirements due to a disability/medical condition or sincerely held religious belief may apply for a reasonable accommodation during the post-offer process. Individuals with approved accommodations will be subject to frequent COVID-19 testing.

Candidates responding to this posting must currently possess the eligibility to work in the United States. No third parties please.

Employment will be contingent on candidate clearing pre-employment drug screen and background check.

Chipton-Ross provides equal employment opportunities to all employees and applicants for employment without regard to race, color, creed, religion, national origin, sex (including pregnancy), age, disability, sexual orientation, gender identity and/or expression, protected veteran status, genetic information, or any other characteristic protected by Federal, State or local law. This policy governs all areas of employment at Chipton-Ross, including recruiting, hiring, training, assignment, promotions, compensation, benefits, discipline, and terminations.