209835 - Digital Circuit Design Engineer 3
$46.13 to $58.40 DOE
12 months

Chipton-Ross is seeking multiple Digital Circuit Design Engineer 3's for a contract opportunity in Chandler, AZ.

• Designing, implementing and testing complex digital, mixed signal, and analog circuit card assemblies for aerospace environment.
• Schematic entry (Cadence Capture CIS), Circuit Simulation (PSpice), Programmable logic design (VHDL) & verification (ModelSim/QuestaSim).
• Hardware troubleshooting / software debugging (Assembly, C++, C#).
• Helping develop the team, mentoring other engineers / interns.
• Writing specifications, user’s manuals, test plans and other technical documents.

Bachelor’s or Master’s, degree in Electrical Engineering, Computer Engineering, or related fields and 5+ years of related professional experience in digital design and related fields.
Available to work on site in Chandler, AZ.
Skillsets We're Looking For:
. Some form of Schematic Capture/PCB Layout Software:
o Knowing at least of 1 of these is required (We Use OrCAD CIS Capture so a huge plus if
they have that):
. OrCAD CIS Capture / OrCAD System Capture / Allegro / Mentorgraphics / Altium
Designer / KiCAD
NOTE: Virtuoso or Cadence are not the same thing and are not skillsets used here. They're tools used for commercial industries such as Microchip, Intel, TSMC, etc.
. Software/Firmware Development Software:
o Experience either developing or modifying logic or software written in one of the
following languages is desirable:
. C++/C#, VHDL/Verilog/SystemVerilog, Assembly
. Note: Verilog-A is not the same thing as
what's listed above and not a skillset we can use.
. Experience with 1 or more of the following Digital Logic Devices:
o Lattice, Xilinx, Altera, Intel, Microsemi, Microchip, Actel
Spartan, Certus, IGLOO, Agilex, Stratix. These are all acceptable as they belong to the families listed above.
. Experience with some form of circuit simulation software:
o Knowing how to use at least 1 of these is crucial to success here:
. PSpice, LTSpice
. Note: HSpice or Spectre are not the
same thing and are unfortunately not tools we utilize here. These would be tools utilized by commercial industries such as Microchip, Intel, TSMC, etc.
. Familiarity with multiple communications protocols:
. SerDes, SPI, I2C, Ethernet, 10/100 Eth, GbE, RS-422, LVDS, PCI-E / PCI / PCI
Express, USB, HDMI, DisplayPort, Fiber
. Familiarity with multiple device types is desirable:
. Microcontrollers (PIC), FPGAs, Digital Signal Processors (DSPs), Microprocessors
(PowerPC, ARM, RISC-V/RISC-5), DDR5/DDR4/DDR3, System on Chip (SoC),
SRAM, ADC/A2D, DAC/D2A, Application Specific Integrated Circuits (ASICs)

• Digital logic design and simulation.
• Analog design and simulation experience.
• Fiber / SpaceFibre familiarity.
• Mixed signal design.
• Power and Signal Integrity (Sigrity, HyperLynx).
• High-speed digital layout experience.
• Familiarity with CADENCE Allegro design environments (Schematic, Simulation, PWB layout).
• FMEA, Reliability analyses.
• Generate and review the technical content of test procedures, drawings, engineering specifications, reports, Engineering Change Requests, and other documentation.
• Design verification using software such as ModelSim and Open-Source VHDL Verification Methodology (OSVVM).
• Motivated self-starter and good at multi-tasking.
• Familiarity with Jira and Agile.
• Exceptional communication, teamwork, and leadership skills.

Bachelors Degree is required.
School must be accredited.

9/80 workweek. Position is on site.

Applicants responding to this position will be subject to a government security investigation and must meet eligibility requirements by currently possessing the ability to view classified government information.

Employment will be contingent on clearing a drug screen and background check. Both must clear prior to start date.

Kevin Suk
420 Culver Boulevard
Playa Del Rey, CA 90293

Phone: (310) 414-7800 x230 or (800) 927-9318 x230

Candidates responding to this posting must currently possess the eligibility to work in the United States. No third parties please.

Employment will be contingent on candidate clearing pre-employment drug screen and background check.

Chipton-Ross provides equal employment opportunities to all employees and applicants for employment without regard to race, color, creed, religion, national origin, sex (including pregnancy), age, disability, sexual orientation, gender identity and/or expression, protected veteran status, genetic information, or any other characteristic protected by Federal, State or local law. This policy governs all areas of employment at Chipton-Ross, including recruiting, hiring, training, assignment, promotions, compensation, benefits, discipline, and terminations.